The present invention relates generally to clock recovery and in particular the present invention relates to phase lock loop and transconductance circuitry for recovering a clock from high data rate signals.
Clock and data recovery in high speed data communication systems require receiver circuits which can adjust an internal oscillator to a frequency and phase of the communicated data. For a description of clock recovery, see C. R. Hogge, xe2x80x9cA Self Correcting Clock Recovery Circuit,xe2x80x9d IEEE, J. Lightwave Technol. LT-3 1312 (1985). Hogge describes a receiver circuit which adjusts a recovered clock signal to center the clock signal transitions in a center of the communicated data signal.
The receiver circuits typically require a phase lock loop circuit to acquire the clock signal from the transmitted data. Phase lock loop circuits adjust an internal oscillator to match a phase of an externally supplied reference signal, such as the received data signal. These phase lock loop circuits compare the reference signal to the internal oscillator signal and provide an output which is used to adjust the oscillator. For example, a parallel digital phase lock loop architecture is described in Fiedler et al., xe2x80x9cA 1.0625 Gbps Transceiver with 2x-Oversampling and Transmit Signal Pre-Emphasis,xe2x80x9d ISSCC 1997 Dig. Tech. Papers, 238 (1997).
High speed data recovery in a communication system operating in excess of 1 GHz requires high speed components, a speed which is difficult to achieve in complementary metal oxide semiconductor (CMOS) fabrication. In particular, current CMOS fabrication sizes of about 0.25 to 0.35 micron have NMOS transistors with a frequency cutoff ft of about 10 to 15 GHz. Thus, processing a signal with a frequency of about 1.25 GHz pushes the transistors to their limitations. Further, gain control in a conventional receiver circuit adjusts the input signal prior to processing with a phase lock loop. Using CMOS processing, accurately adjusting the gain of the high frequency input data is not presently possible. The economics of IC fabrication create a need for a solution to high speed clock recovery using CMOS technology.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for a CMOS receiver circuit capable of recovering a clock signal and data in a high speed data communication system. Further, there is a need for a receiver which can adjust gain to changes in the communication data voltage.
The above mentioned problems with high speed data communication receiver circuits and other problems are addressed by the present invention and will be understood by reading and studying the following specification.
In particular, the present invention describes a high speed data receiver comprising a phase detector circuit coupled to receive a high speed input data signal and provide an analog voltage output indicating a signal phase difference between the high speed input data signal and a second input signal. A transconductance circuit is provided to convert the analog voltage output into an analog output current. An oscillator provides the second input signal to the phase detector in response to the analog output current.
In another embodiment, a high speed data receiver comprises a phase detector circuit coupled to receive a high speed input data signal and provide differential analog voltage outputs indicating a signal phase difference between the high speed input data signal and a second input signal. The receiver further includes a transconductance circuit coupled to the phase detector circuit for converting the differential analog voltage outputs into an analog output current, an oscillator coupled to the transconductance circuit and providing the second input signal to the phase detector in response to the analog output current, and a phase frequency detector circuit coupled to receive an output of the oscillator and provide an output indicating a frequency difference between the output of the oscillator and a reference clock signal. A charge pump circuit provides an output signal in response to the phase frequency detector circuit. The charge pump output signal is coupled to an input of the oscillator.